The present invention relates to improvements in a mixed signal integrated circuit containing both an analog circuit and a digital circuit and in a test method therefor.
In the today's industrial world, efficient testing of connections between a plurality of circuits on a printed circuit board is a goal to be attained with a considerably high priority. Under such circumstances, the IEEE (Institute of Electrical and Electronics Engineers, Inc.) adopted a boundary scan technique as a standard in 1990 (IEEE Std 1149. 1-1990). Although the standardized technique is useful for a digital circuit, a printed circuit board actually used as a product contains both an analog circuit and a digital circuit. Hence, it has been difficult to test connections between all circuits on the printed circuit board by using the foregoing boundary scan technique.
To overcome the difficulty, the technique of testing an analog circuit or a mixed signal integrated circuit (analog boundary scan) has conventionally been proposed in, e.g., ITC 1993 Paper 15.2 Structure and Metrology for an Analog Testability Bus, Kenneth P. Parker et al. and in Japanese Laid-Open Patent Publication No. 6-347517. Owing to the technique, it has become possible to test device interconnections or an analog discrete component present between the devices in a mixed signal integrated circuit by using no test probe at all or only a reduced number of test probes.
FIG. 15 shows a conventional integrated circuit device 601 using the foregoing analog boundary scan technique. As shown in the drawing, the integrated circuit has: an analog core circuit 602; a digital core circuit 603 connected to the analog core circuit 602 by a connecting line 608; a plurality of analog boundary scan cells 605 disposed around the analog core circuit 602; a plurality of digital boundary scan cells 606 disposed around the digital core circuit 603; a single scan path 607 connecting in series the analog and digital boundary scan cells 605 and 606; an analog test bus 611 for transmitting analog signals for testing (analog test data) to the analog boundary scan cells 605; a test controller 604; an data input terminal 609 for receiving test data; an output terminal 610 for outputting a test result; and an analog test terminals 612 and 613 for receiving and outputting the analog test data.
The digital core circuit 603 receives digital test data which has been inputted to the digital boundary scan cells 606 through the data input terminal 609 and the scan path 607. On the other hand, the analog core circuit 602 is brought into a testable state by test control data for placing the analog core circuit 602 under test which has been inputted to the analog scan cells 605 through the data input terminal 609 and the scan path 607, while receiving analog test data from the analog boundary scan cells 605, which has been inputted to the analog boundary scan cells 605 through the analog test terminals 612 and 613 and the analog test bus 611.
However, in the case of testing, e.g., only the analog core circuit 602 in the conventional integrated circuit, it is necessary to shift sets of test control data in the analog boundary scan cells 605 through the digital boundary scan cells 606, since the scan path 607 contains the analog and digital boundary scan cells 605 and 606. In other words, it is inevitable to concurrently perform the writing of test control data to the analog boundary scan cells (input cells and output cells) 605 of the analog core circuit 602 and the writing of test control data to the digital boundary scan cells (input cells and output cells) 606 of the digital core circuit 603.
Thus, even when only a part of the integrated circuit (e.g., the analog core circuit 602) is to be tested, it is necessary to shift sets of scan test data in a scan chain not to be tested (the digital boundary scan cells 606 for the digital core circuit 603), so that a test pattern is elongated and enlarged while test time is increased disadvantageously. In addition, the process of automatically generating test data for boundary scan is also complicated and elongated in time.